JD基本信息
岗位职责
1、独立完成较复杂逻辑项目/模块的特性分析、设计、编码、仿真和上板调试,相关问题的定位与解决,配套文档的编写;
2、及时定位解决客户反馈或内部测试中发现的逻辑相关问题;
3、与周边同事通力合作密切配合,有领导能力能够负责整个产品/项目的协调和端到端交付者优先考虑;
4、能有效应对一段时期的较重的进度和工作量压力,按时保质交付;
1.Independently complete the characteristic analysis, design, coding, simulation and on-board debugging of relatively complex logic projects/modules, locate and solve related problems, and write supporting documents.
2.Timely locate and solve logic-related problems found in customer feedback or internal testing.
3.Cooperate closely with colleagues around. Those with leadership skills and being able to be responsible for the coordination and end-to-end delivery of the whole product/project will be given priority.
任职要求
1、具有良好的数字电路基础知识,有较强的逻辑思维能力,工作踏实细心;
2、精通FPGA设计开发的专业能力,重点包括各类以太网接口规范和实现方法、高速大带宽报文处理技术、流调度技术、高速串行接口和高速RAM接口等等,熟悉Verilog HDL语言;
3、有很好的团队协作意识和沟通能力,抗压能力强,自我管理能力强;
4、不少于2年的以太网通信相关领域FPGA开发经验,在相关大企业研发部门工作者优先考虑;
5、良好的英文读写能力,能熟练阅读英文技术文档和专业文献。
1.Have a good basic knowledge of digital circuits, strong logical thinking ability, and be down-to-earth and careful in work.
2.Be proficient in the professional ability of FPGA design and development, be familiar with device structures, and be skilled in using tools such as Vivado, Quartus, VCS, and Modelsim.
3.Have experience in the design of high-speed external memory interfaces, such as DDR, QDR, RLDRAM, etc.
4.Have experience in using high-speed serial interfaces, such as 100GMAC, 40GMAC, PCIe-DMA, Interlaken, etc.
5.Be familiar with Ethernet protocols.
6.Have a good sense of teamwork and communication skills, strong stress resistance, and strong self-management ability.
7.Have worked for more than 8 years and been engaged in FPGA development in the communication-related fields.
工作城市:
美国,招聘1人,详细地址:海外地点可以再定