职位描述： 1.致力打造世界一流的深度学习硬件计算平台， 跟踪深度学习及系统硬件架构的发展，设计开发高性能低功耗的架构、芯片及硬件产品。 2.针对集团业务发展需求，与阿里巴巴的算法和业务团队和作， 规划设计与业务相匹配的异构计算软硬件产品构架。 3.确保前端设计的质量检查，以及跟后端流程的协做。 1. Bluild the world-cdas dep leaming platforms.folow dosely with the latest inovations on dep leaming algorithms and acelerator archtectre., Architect and design deep leaming Hwacceleration platform for high performance and low power. 2. Target at the specific computation neds ofdriving busines qrowth. colaborate with xx algorithm and businesteams, Architec and develope heterogenous platfomis that drive busines growth. 3. Own front-end design quality checks and reviews to present the physical design team with high-quality RTL.

职位要求： 至少3年以上ASIC，并满足以下一个或多个方向 1.熟悉芯片设计流程，并有参与流片的经验。 2.熟悉RTL综合,Floorplan 到后端时序收敛的流程，16nm及以下优先考虑。 3.问题解决能力强而目全面,具优秀团队沟通协作能力。 4.使用过设计验证自动工具以及脚本的经验。 5.熟悉主要总线协议，CPU,以及常用数字 IP, SerDes,Phy，参与过芯片顶层整合，大型芯片设计经验者优先。 ASIC Design Enaineer should have related B.s, with 5+ years of ASIC/FPGA experience, or M.s.EE with 2+ years, and satisfy one of the folowing qualfication sets 1. Familiar the full flows of ASIC/FPGA design and participated the actual tape-out process. 2. Familiar the RTl synthesis, Floorplan to timing closure with the process technology at least 16nm or smaller. 3. Strong problem solving abilities. Great communication and collaboration skils to interact with other team members. 4.Exposure to desiqn and verification tools and scripting lanquage. 5. familiar AMBA protocol, CpU, knowledgable about digital Ip, SerDes, Phy, participated the chip integration, Server grade design will be a plus.